With the continuously scaling of semiconductor devices, contact holes (CAs) and corresponding contact portions are becoming smaller, with the distances therebetween also being reduced. There are following problems with the prior art for manufacturing a small contact hole/contact: (1) As the etching depth on a gate is different from that in source/drain regions, short circuits likely occur between the contact hole and the gate; (2) As the etching depth in the source/drain regions is large whereas the size of openings thereof is small (i.e., it has a small width-to-height ratio), a number of process defects such as underetching, cavities in metal-filling plugs, and so on may be caused. Thus, the selection of processes is restricted, and the parasitic resistance increases.
To solve the above problems, the applicant has proposed the following process (Chinese Application No. 200910092514.3, Attorney Docket No. IB094429). Specifically, a first interlayer dielectric layer is deposited on a semiconductor substrate with a transistor structure (including a gate and source/drain) formed thereon, and then is subjected to planarization such as Chemical Mechanical Polishing (CMP) so that the gate is exposed. Then, contact holes are formed in the first interlayer dielectric layer at positions corresponding to the source/drain, and are filled with a conductive material such as metals, so as to form bottom contacts coming into contact with the source/drain. Next, a second interlayer dielectric layer is further deposited, and contact holes are further formed in the second interlayer dielectric layer at positions corresponding to the gate and the source/drain and are also filled with a conductive material such as metals, so as to form top contacts coming into contact with the gate and the source/drain.
Thus, the contacts are formed in two steps, reducing the difficulty in forming the contacts just by a single step. Further, in forming the top contacts, the contact holes at the gate and source/drain regions have the same etching depth. Therefore, the problems in the prior art as described above can be overcome.
However, if this process is applied to the replacement gate process, generally filling of gate metal and filling of metal in contact holes are carried out respectively; further, the gate metal and the metal filled in the contact holes are different from each other (see the above application No. 200910092514.3 filed by the applicant). Furthermore, a CMP process is necessary after the bottom contacts coming into contact with the source/drain are formed. Such a CMP process is complicated and has very stringent requirements thereon.
In view of the above, there is a need for a novel semiconductor device and a method of fabricating the same, whereby it is possible to simplify the process flows.